Computer architecture and logic design

Digital Design & Comp. Arch: L2: Transistors, Gates, Combinational Logic (Spring 2026)

Seminar in Comp. Arch. - L1: Introduction & Logistics (Spring 2026)

Digital Design & Comp. Arch.: Lecture1: Introduction: Fundamentals, Transistors, Gates (Spring 2026)

OXMIQ CEO Raja Koduri on Re-Architecting the GPU Stack: From Atoms to Agents

MCCSys-4: 4th Workshop on Memory-Centric Computing Systems, held with HPCA 2026 - 1 February 2026

4th Data Prefetching Championship (DPC4) - HPCA 2026 - Sydney - Feb 1, 2026

Software-Defined Systems

Le Futur CPU qui Fait Trembler AMD, Intel et ARM ? RISC-V est DEJA dans TON PC ?

The Future CPU That Will Make AMD, Intel, and ARM Tremble? Is RISC-V ALREADY in YOUR PC?

Comp. Arch. - Lecture 27: VLIW Architectures (Fall 2025)

Comp. Arch. - Lecture 26: Parallelism, Heterogeneity, and Bottleneck Acceleration (Fall 2025)

A Quantitative Study of Locality in GPU Caches for Memory-Divergent Workloads

1st SAFARI Conference, 2025

Comp. Arch. - Lecture 24: On-Chip Networks & Router Design (Fall 2025)

Comp. Arch. - Lecture 23: Interconnects (Fall 2025)

Comp. Arch. - Lecture 22: Virtual Memory (Fall 2025)

Comp. Arch. - Lecture 20: Prefetching III and Multiprocessors (Fall 2025)

Comp. Arch. - Lecture 19: Prefetching and Prefetcher Design II (Fall 2025)

Comp. Arch. - Lecture 18: Simulation and Prefetching (Fall 2025)

CONCEPT OF BOOTH ALGORITHM | COA | LECTURE 01 BY MS. KAJAL KAUSHAL | AKGEC

Comp. Arch. - Lecture 14: Cutting-Edge Research in Memory Robustness & Security (Fall 2025)

Comp. Arch. - Lecture 10: Memory Controllers II, Service Quality and Performance (Fall 2025)

Raúl Murillo: “Reducir datos y acelerar cálculos con menos energía”

Raúl Murillo: “Reducing data and accelerating calculations with less energy”

Computer Architecture - Lecture 9: Memory Latency II and Memory Controllers (Fall 2025)

Can We Do Better? - Keynote Talk at MICRO 2025 - Prof. Onur Mutlu

MICRO 2025: 1st Workshop on Virtuoso: Infrastructure for Evaluating Novel HW/OS Interfaces

MICRO 2025: 1st Workshop on Architecture for Health (Arch4Health)

Computer Architecture - Lecture 8: Memory Latency (Fall 2025)

Computer Architecture - Lecture 7: Data Retention in Memory (Fall 2025)

Computer Architecture - Lecture 6: Memory-Centric Computing III (Fall 2025)

Computer Architecture - Lecture 5: Memory-Centric Computing II (Fall 2025)

Computer Architecture - Lecture 4: Memory-Centric Computing I (Fall 2025)

Computer Architecture - Lecture 3: Memory Systems: Challenges and Opportunities (Fall 2025)

Computer Architecture - Lecture 2: Memory Systems and Course Logistics (Fall 2025)

Seminar in Computer Architecture - Lecture 2: Memory-Centric Computing (Fall 2025)

Computer Architecture - Lecture 1: Introduction and Basics (Fall 2025)

The World's First Ternary Computer

Seminar in Computer Architecture - Lecture 1: Introduction and Logistics (Fall 2025)

Hardware Constraints

Computer Architecture 101 and its Future

Why Light Will Change Computers Forever